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每日更新;

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何泽隆
2024-05-08 20:19:59 +08:00
parent 3ccfca4b32
commit c082492f22
1 changed files with 9 additions and 5 deletions
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14
source/utl_upgrade.py
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@@ -196,7 +196,7 @@ def test2():
buffer2_en = file_encryption(buffer2) buffer2_en = file_encryption(buffer2)
pass pass
def test3(): def test3(path_bin):
""" 完整升级包生成测试 """ """ 完整升级包生成测试 """
config = { config = {
'file_type': [0x10, 0x01], # Xilinx-Demo 自机升级文件 'file_type': [0x10, 0x01], # Xilinx-Demo 自机升级文件
@@ -217,19 +217,23 @@ def test3():
# 'flash_addr': 0x3E8020, # 程序起始地址 # 'flash_addr': 0x3E8020, # 程序起始地址
# 'flash_size': 0x005FC0, # 程序空间大小 # 'flash_size': 0x005FC0, # 程序空间大小
} }
path_bin = Path("F:\\Work\\FPGA\\Test\\Vivado\\test_update\\test_update.vitis\\upgrade_system\\Debug\\sd_card\\BOOT.BIN")
header, data_b, _ = make_datafile2(path_bin, config, header_len=512) header, data_b, _ = make_datafile2(path_bin, config, header_len=128)
header_512, data_b_512, _ = make_datafile2(path_bin, config, header_len=512)
print("Upgrade file generated successfully.") print("Upgrade file generated successfully.")
print(f"\t header_length={len(header)}, bin_length={len(data_b)}[{hex(len(data_b))}]") print(f"\t header_length={len(header)}, bin_length={len(data_b)}[{hex(len(data_b))}]")
print(f"\t file md5: {trans_list_to_str(config['md5'])}") print(f"\t file md5: {trans_list_to_str(config['md5'])}")
file1 = path_bin.parent / (path_bin.stem + '_h512.dat') file1 = path_bin.parent / (path_bin.stem + '.dat')
file1.write_bytes(header + data_b) file1.write_bytes(header + data_b)
file2 = path_bin.parent / (path_bin.stem + '_h512.dat')
file2.write_bytes(header_512 + data_b)
if __name__ == "__main__": if __name__ == "__main__":
path_bin = Path("F:\\Work\\FPGA\\Test\\Vivado\\test_update\\test_update.vitis\\upgrade_system\\Debug\\sd_card\\BOOT.BIN")
# test1() # test1()
# test2() # test2()
test3() test3(path_bin)
pass pass